1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly relates to a semiconductor memory device including a twin-cell type DRAM (Dynamic Random Access Memory) characterized by low consumption power suited for portable equipment.
2. Description of the Background Art
In recent years, as the performance of portable terminals including cellular phones have enhanced, demand for mass storage RAM""s rises. A portable equipment, which is driven by batteries, has employed, as an RAM, an SRAM (Static RAM) capable of realizing low consumption power. However, the SRAM cannot satisfy and follow up mass storage demand accompanying enhanced system function and it has become, therefore, necessary to mount a DRAM, which can easily realize mass storage, on a portable equipment.
Nevertheless, because of the structural characteristics of the DRAM, the state of the DRAM in which memory cells hold data is off balance and the data stored in the memory cells disappear when a certain period of time passes. Due to this, the DRAM is required to rewrite the stored data (or refresh the data) before the data disappears. This refresh operation consumes current for changing and discharging bit lines. That is why a DRAM has a higher consumption current than an SRAM which can dispense with a data refresh operation.
To mount a DRAM on a portable equipment in place of an SRAM, it is necessary to reduce current consumed by this refresh operation. To this end, it is the most effective to lengthen data retention time and to decrease the number of times (frequency) of the refresh operation.
FIG. 5 shows a state of a DRAM memory cell right after xe2x80x9cHxe2x80x9d data has been written to the cell. FIG. 6 shows a state of the DRAM memory cell right after xe2x80x9cLxe2x80x9d data has been written to the cell.
Referring to FIGS. 5 and 6, the DRAM memory cell has a 1-transistor, 1-capacitor structure consisting of a memory transistor and a capacitor. The memory transistor is formed in a p type well region 1a electrically isolated by isolation regions 2 of a semiconductor substrate 1. This memory transistor includes a pair of source drain regions 3 formed on the surface of p type well region 1a and a gate electrode (word line) 5 formed in a region put between paired source and drain regions 3 through a gate insulating film. The storage node (lower electrode) 7 of the capacitor is electrically connected to one of paired source and drain regions 3 and a bit line 12 is electrically connected to the other of paired source and drain regions 3. Also, a p+ region 21 is formed on the surface of p type well region 1a. 
To simplify the drawings, the cell plate (upper electrode) of the capacitor and the like are not shown in FIGS. 5 and 6.
In FIG. 5, the potential of storage node 7 right after data has been written is Vcc (which is normally about 2V), the potential of bit line 12 is xc2xd Vcc, the potential of the substrate (p type well region 1a) is Vbb (which is normally about xe2x88x921V) and the potential of word line 5 is GND (=0V). In this state, the memory transistor is turned off.
An inverse bias of |Vcc|+|Vbb| (3V in this case) is applied to the pn junction between storage node 7 and the substrate (p type well region 1a). Due to this, a junction leak current flows from storage node 7 to substrate 1a and the potential of storage node 7, therefore, gradually decreases. If the potential of storage node 7 decreases from Vcc to be lower than the potential of bit line 12, i.e., xc2xd Vcc, the stored data is erroneously recognized as not xe2x80x9cHxe2x80x9d but xe2x80x9cLxe2x80x9d data, meaning that the stored data is destroyed.
Meanwhile, in FIG. 6, the potential of storage node 7 is GND (=0V). In this case, too, an inverse bias of |GND|+|Vbb| (1V in this case) is applied to the pn junction between storage node 7 and substrate 1a and a junction leak current flowing from storage node 7 to substrate 1a exists. However, since the potential of storage node 7 is originally lower than the potential of bit line 12, i.e., xc2xd Vcc, the potential of storage node 7 does not exceed xc2xd Vcc. Due to this, xe2x80x9cLxe2x80x9d data is not destroyed.
It is a twin-cell system that is intended to considerably enhance data retention characteristics using the characteristics that xe2x80x9cLxe2x80x9d data is not destroyed. FIG. 7 is a typical view of DRAM cells according to the twin-cell system.
Referring to FIG. 7, the twin-cell system is such that two memory cells (a pair of memory cells) constitute one bit. If xe2x80x9cHxe2x80x9d data is stored in a certain memory cell, xe2x80x9cLxe2x80x9d data is stored in a memory cell which forms, together with the certain memory cell, a memory cell pair. If xe2x80x9cLxe2x80x9d data is stored in a certain memory cell, xe2x80x9cHxe2x80x9d data is stored in a memory cell which forms, together with the certain memory cell, a memory cell pair.
Each of the paired memory cells is electrically connected to each of a pair of bit lines and also electrically connected to each of two word lines selected simultaneously. It is noted that the paired bit lines are electrically connected to a sense amplifier amplifying a small potential difference generated between the paired bit lines to a power supply voltage.
FIG. 8 is a graph showing the comparison between an ordinary single-cell type memory and a twin-cell type memory with respect to retention characteristics. Referring to FIG. 8, the horizontal axis is pause time since data is written until the data is read and the vertical axis is total failure bit counts per chip. As a result of the comparison, it is seen that if the single-cell type memory is formed into the twin-cell type memory, retention characteristics is improved about fourfold.
However, the twin-cell type memory constitutes one bit out of two cells and has a larger chip size than that of the single-cell type memory, thereby disadvantageously pushing up cost. In case of the twin-cell type memory, the area of a memory cell part occupies about 50% of a chip area. Due to this, if the area of the memory cell part doubles, the chip area of the twin-cell type memory becomes 1.5 times as large as that of the single-cell type memory.
It is an object of the present invention to provide a twin-cell type semiconductor memory device capable of reducing the area of a memory cell part while maintaining data retention characteristics.
A semiconductor memory device according to the present invention is a semiconductor memory device having a memory array structure in which a plurality of word lines and a plurality of bit lines for selecting a predetermined memory cell are arranged to intersect with one another, characterized by including: two memory cells constituting one bit; and a sense amplifier electrically connected to both of the two memory cells constituting the one bit, through the bit lines. A first word line electrically connected to one of the two memory cells constituting the one bit and a second word line electrically connected to the other one of the two memory cells are arranged opposite each other across the sense amplifier.
According to the semiconductor memory device of the present invention, the twin-cell system wherein two memory cells constitute one bit is adopted and data retention time can be, therefore, lengthened. This can decrease the number of times (frequency) of data refresh operation and reduce current consumed by the refresh operation. It is, therefore, possible to reduce the consumption current of DRAM.
Further, since the first and second word lines are arranged opposite each other across the sense amplifier, the two memory cells constituting one bit are naturally arranged opposite each other across the sense amplifier. As a result, there is no need to provide two bit lines, forming a bit line pair having a small potential difference at the time of reading data, on one side of the sense amplifier. This enables restrictions to pattern arrangement to be relaxed, the memory cells to be arranged more compactly than the conventional memory and an area occupied by the memory cells in a chip to be smaller than that in the conventional case.
Preferably, in the semiconductor memory device stated above, the first and second word lines are electrically connected to each other and electrically connected to a common word line driver.
By doing so, it is possible to simultaneously select and drive the two memory cells constituting one bit.
Preferably, in the semiconductor memory device stated above, a pitch size of the word lines and a pitch size of the bit lines are 2xc3x97F, respectively, a plane area occupied by one memory cell is 6xc3x97F2.
By doing so, it is possible to reduce the area occupied by the memory cells in a chip compared with that in the conventional case.
Preferably, in the semiconductor memory device stated above, each memory cell is a DRAM memory cell.
By doing so, it is possible to obtain a DRAM capable of considerably improving retention characteristics and reducing the rate of the area of a memory cell part which occupies a chip area compared with that in the conventional case.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.